NI PXIe-6363 AIO/DIO/Counter/Timing PXI Board

This module integrates 32 single-ended/16 differential analog inputs (16-bit ADC, maximum sampling rate of 2 MS/s per channel), 4 analog outputs (16-bit DAC, maximum update rate of 2.86 MS/s per channel), 48 bidirectional digital I/O channels, and 4 32-bit counters/timers, enabling a complete multi-function measurement and control system on a single standard 3U PXI module.

The PXIe-6363 AIO/DIO/Counter/Timing PXI Board features an NI-STC3 timing and synchronization chip, providing independent analog and digital timing engines and retriggered measurement task capabilities. It supports 8 DMA channels for high-speed data streaming with zero CPU overhead. The module uses a PXI Express x1 native interface, compatible with PXI Express specification 1.0, and can be inserted into x1 or x4 PXI Express/hybrid slots. It fully utilizes the 100 MHz differential reference clock and differential star trigger lines on the PXI Express backplane to achieve sub-nanosecond multi-module synchronization.

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Description

The NI PXIe-6363 is a high-performance, multi-functional I/O data acquisition module for the PXI Express platform, part number 781056-01.This module provides engineers and scientists with a compact solution that integrates analog inputs, analog outputs, digital I/O, and counters/timers in a single PXI Express slot, suitable for a wide range of applications from laboratory R&D to production line automation.

The PXIe-6363 AIO/DIO/Counter/Timing PXI Board fully leverages the high bandwidth and low latency of the PXI Express bus, enabling high-throughput continuous data streaming through its native x1 PCI Express interface and 8 DMA channels, thus preventing the CPU from becoming a bottleneck for data transfer.The onboard NI-STC3 timing controller provides a 100 MHz time base and a phase-locked loop (PLL) that can be locked to a 100 MHz differential reference clock on the PXI Express backplane, enabling high-precision synchronization between multiple modules.

NI Multifunctional DAQ: Three Generations of Evolution

Specifications- PXIe-6363 AIO/DIO/Counter/Timing PXI Board

Within the X-series product lineup, the PXIe-6363 is positioned as a flagship model featuring high channel count and high sampling rate:

The PXIe-6363 AIO/DIO/Counter/Timing PXI Board offers a balanced configuration of 32 analog inputs, 4 analog outputs, and 48 digital I/Os, making it ideal for applications requiring simultaneous multi-channel acquisition and generation. For additional AI channels, NI recommends upgrading to the PXIe-6365 or PXIe-6375

Advantages of the PXIe-6363

• High-performance, multi-functional PXIe module: 16 analog inputs (16-bit, 2 MSPS synchronous sampling), 4 analog outputs (2.86 MSPS), 24 digital I/Os, 4 counters/timers—extremely high single-module integration.
• X-series architecture advantages: Equipped with the NI-STC3 timing engine and NI-MCal calibration technology, gain error ±0.01%, offset drift 2 μV/°C, achieving instrument-grade absolute accuracy.
• PCIe Gen 1 x4 bus interface: Total bandwidth approximately 1 GB/s, supports multi-core parallel processing, driver optimized for multi-core CPUs, suitable for high-speed disks and real-time control.
• Complete signal chain capabilities: Analog inputs support ±200mV~±10V multi-range, 4-wire differential input; analog outputs ±11V/40mA drive capability; onboard PLL supports precise clock synchronization and triggering.

NI-STC3 Timing and Synchronization Technology

The core timing engine of the PXIe-6363 AIO/DIO/Counter/Timing PXI Board is the NI-STC3 chip, a signature technology that distinguishes the X-series devices from their predecessors. The NI-STC3 provides the following key capabilities:

• Independent analog and digital timing engines: Analog inputs, analog outputs, and digital I/O subsystems can operate independently without interference, truly achieving parallel acquisition and generation.
• Retrievable measurement tasks: Supports multiple trigger starts within a single task, allowing for repeated acquisition without software intervention.
• 100 MHz internal time base: Timing resolution reaches 10 ns, far exceeding the 12.5 ns of the previous M series.
• Onboard PLL: Can be locked to reference clock sources such as PXIeCLK100 (100 MHz), PXISTAR (10/20 MHz), and PFI (10/20 MHz), achieving high-precision synchronization across multiple devices.

High-throughput PXI Express Native Interface

The X-series devices utilize native PCI Express interfaces (non-bridged), providing full x1 link bandwidth (theoretically 250 MB/s per direction), instead of being limited to the traditional PCI's 132 MB/s via a PCI-to-PCIe bridge chip. Eight DMA channels (distributed-collection mode) provide parallel data streams for AI, AO, DI, DO, and four counters, requiring no CPU intervention.

NI-MCal Full-Range Calibration Technology

The X Series employs NI-MCal self-calibration technology, covering all input ranges. Through an on-chip high-precision voltage reference and self-calibration circuitry, it corrects gain and offset errors for each range during each internal calibration. The calibration interval is extended from 1 year for the E Series to 2 years, reducing maintenance costs and downtime.

Multi-core optimized driver software

The included NI-DAQmx driver is optimized for multi-core PCs and supports development environments such as LabVIEW, LabWindows/CVI, Measurement Studio (.NET), Python (via the NI-DAQmx Python API), and MATLAB. NI-DAQmx 9.0 and later versions introduce multi-device task functionality, allowing multiple devices to be included in a single codebase, with drivers automatically managing sampling clock sharing and synchronization.

Abundant triggering and Synchronization Options

PXIe-6363 provides comprehensive triggering capabilities:

• Analog Trigger: 1 channel, source can be AI<0..31> or APFI<0,1>, supports analog edge triggering, hysteresis-based analog edge triggering, and analog window triggering.
• Digital Trigger: Source can be any PFI, PXIeDSTAR<A,B>, PXITRIG, or PXI_STAR.
• Inter-device Trigger Bus: Multi-module synchronization is achieved through PXITRIG<0..7>, PXISTAR, and PXIe_DSTAR<A,B/C> signals on the PXI backplane
• Dejitter Filtering: 90 ns / 5.12 μs / 2.56 ms / Custom / Disabled, each input can be configured independently.

Functions

The PXIe-6363's analog input subsystem is based on a 16-bit successive approximation ADC, which scans up to 32 single-ended or 16 differential channels via a multiplexer.

• Programmable Input Range: 7 programmable ranges (±0.1 V to ±10 V), covering signal ranges from millivolts to ±10 V
• Multiplexed Scanning: Onboard NI-PGIA (Programmable Gain Instrumentation Amplifier) ​​ensures rapid stabilization after each channel switch
• Hardware Timing Acquisition: Supports both hardware timing single-point and waveform acquisition modes
• DMA Data Transfer: 2,047-sampling-depth FIFO combined with DMA transfer prevents data overflow
• Analog Trigger: Supports three trigger modes: analog edge, analog edge with hysteresis, and analog window
• Overvoltage Protection: ±25 V when device is on, ±15 V when device is off (up to 2 AI pins simultaneously)

Four independent 16-bit DAC channels support synchronous updates; each channel has its own DAC but shares an output FIFO with an 8,191-sample depth.

• Multi-channel synchronous update: 4 channels with a maximum synchronous output of 1.25 MS/s/ch
• Flexible output range: ±10 V, ±5 V, or external reference (APFI 0,1)
• Waveform modes: Supports three modes: non-periodic waveform, onboard FIFO periodic regeneration, and host buffer dynamic update of periodic waveforms
• High drive capability: ±5 mA output current, 0.2 Ω output impedance
• Fast stabilization: 15 ppm full-amplitude transition, 2 μs settling time, 20 V/μs edge slope

48-channel bidirectional digital I/O is divided into three ports

• Port 0 supports hardware-timed digital waveform acquisition and generation, with a maximum clock frequency of 10 MHz
• PFI lines can be used as timing inputs (external sources for AI/AO/DI/DO clocks and triggers) or timing outputs (routing internal signals to the external environment)
• Digital line filter: 160 ns / 10.24 μs / 5.12 ms / Disabled, used for signal dejittering
• Dejitter filter: 90 ns / 5.12 μs / 2.56 ms / Custom / Disabled, independently configurable for each input

Four 32-bit general-purpose counters/timers provide rich measurement and generation capabilities

• Edge counting, pulse measurement, pulse width measurement, half-cycle measurement, period measurement, double-edge interval measurement
• X1/X2/X4 quadrature encoding position measurement (with Z-channel reset), dual-pulse encoding
• Output Functions - Pulse generation, dynamic pulse sequence update, frequency division, isochronous sampling

1-channel frequency generator, reference clock 20 MHz / 10 MHz / 100 kHz, divider 1–16, accuracy 50 ppm.

Shock and Vibration

Software User Manual

NI-DAQmx driver software

• Multi-core Optimization: Fully leverages the parallel computing capabilities of multi-core processors
• Multi-device Tasks: NI-DAQmx 9.0+ supports multiple devices within a single task, automatically managing sampling clock sharing and synchronization
• DMA Data Transfer Management: Automatically transfers data between the onboard FIFO and PC buffer, preventing FIFO overflow/underload
• NI MAX Configuration Tool: Measurement & Automation Explorer provides device discovery, self-test, self-calibration, test panels, and task configuration functions
• Channel Expansion: Supports multi-module channel expansion via PXI Express backplane or RTSI cable

Supported Development Environments

NI LabVIEW, C / C++, Python, C# / .NET, MATLAB, NI LabWindows/CVI

Custom Design

We get it that standard arrangements do not continuously meet one of a kind prerequisites. Our experienced building group gives comprehensive OEM/ODM customization administrations. Whether you require adjusted recurrence ranges, specialized activating alternatives, or custom frame components, we work closely with you to create the idealize arrangement. Our adaptable plan approach guarantees your particular application needs are completely tended to whereas keeping up our quality standards.

Why Choose MXTD?

Proven Experience

With over 12 years in the industry, we understand your challenges and deliver solutions that work.

Quality Assurance

Strict quality control processes ensure every board meets our high standards for reliability and performance.

Comprehensive Support

Our technical team provides ongoing assistance from initial consultation through long-term maintenance.

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Reliable Delivery

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FAQ:

Q: Why do adjacent channels exhibit crosstalk or ghosting during multi-channel high-frequency acquisition?

A:  

• This is because the PXIe-6363 uses a multiplexed ADC architecture, where all AI channels share a single sample-and-hold capacitor (maximum aggregate sampling rate of 1 MS/s). If the impedance of the preceding channel is too high, the residual charge in the capacitor cannot be discharged within the extremely short "convert clock" when switching to the next channel, thus contaminating the data of the subsequent channel.

Solutions: 

Reduce source impedance: It is recommended that the impedance of the preceding series signal source be less than 1 kΩ, or add a voltage follower (impedance matching isolator).

Increase the interval time: Manually increase the conversion clock rate in the NI-DAQmx property node to allow more charging/discharging time for the capacitor.

Add a dummy channel: Insert a physically grounded "dummy channel" between two high-impedance channels to discharge the charge.

Q: What is the maximum voltage that the analog input pins of the board can withstand? Will exceeding the range cause damage?

A: 

The standard measurement range of the PXIe-6363 is ±10V.

Powered-on state (Device On): The maximum operating voltage (signal + common-mode voltage) between each AI channel and AI GND is ±11V; its built-in overvoltage protection can withstand up to ±30V when the device is powered on. Power-off state (Device Off): The maximum withstand voltage is ±15V.

Note: Despite hardware-level overvoltage protection, if the input voltage exceeds ±30V for an extended period, it will still cause permanent thermal damage to the chip. High-voltage testing must be performed with an attenuator or isolation module pre-amplified

Q: Why is the acquired analog signal so noisy when using the ±5V power output from the front panel of the PXIe-6363 to power an external sensor​​​​​​​?

A: 

• The ±5V power supply (D GND as reference ground) comes from a general-purpose switching power rail in the computer/chassis. This power supply is not low-noise linearly regulated and exhibits noticeable sawtooth waves and high-frequency switching noise.

Solution:

Only recommended for driving low-current digital logic chips (such as optocouplers, pull-up resistors, etc.). For high-precision microvolt/millivolt level sensor signals, a separate external linearly regulated power supply (LDO) must be used for excitation power​​​​​​​

Q: The PXIe-6363 claims to have 48 digital I/O channels and supports hardware-level timing control. Why then does it display the message "Channel does not support hardware clock" when configuring high-speed DIO tasks?

A: ​​​​​​​

This is a common misconception. Of the 48 digital pins, only 32 channels of Port 0 (P0.0 to P0.31) support full hardware-timed timing. Port 1 and Port 2 (i.e., PFI 0 to PFI 15 pins) are software-timed (static I/O) channels by default, and their response speed is limited by the execution cycle of the host computer software (typically in milliseconds). If you need to run high-speed PWM, photoelectric encoder speed measurement, or digital waveform generators, you must connect the physical signal lines to the corresponding pins of Port 0, or specify the appropriate PFI hardware timing engine.

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Contact our technical specialists at manager03@mxtdinfo.com  / manager02@mxtdinfo.com for detailed specifications, pricing information, or to discuss your custom requirements. We're committed to delivering the perfect NI PXIe-6363 AIO/DIO/Counter/Timing PXI Board solution for your application needs.